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CD4029

How do I stabilize the pulse widths of the 4029 Binary Counter?

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Asked 2 days ago

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I am working with a CD4029BE on a breadboard. The connections are as follows:

VDD to +12VDC VSS to ground The clock input receives a 3Hz 0 to +12V clock pulse J1-J4 are shorted together, and then shorted to ground Pin 5 (Carry in) to ground Preset Enable shorted to ground Up/Down and Binary/Decimal shorted to +12 to enable upward binary counting

The issue is that at the outputs, Q1-Q4, the outputs count correctly except that the pulse width randomly changes at all the outputs, meaning sometimes Q1 has a 50% duty cycle on/off, but every random number of pulses it will stay high or low for bit longer than it should; the same behavior happens at the other outputs.

I think this could be a stray capacitance issue, but the datasheet doesn’t say anything about where bypass caps might be needed. If I add 0.1 or 0.001u ceramic caps near the power supply connections it affects the pulses at the outputs, but the outputs are still randomly different widths every so often.

I also tried a second 4029 IC that I had, and the same issue happens, but just with different random pulses wider or smaller on the outputs.

Please advise how I can stabilize the outputs of this IC.

Posted below is an image of my clock signal, which comes from the output of a 555 timer. The pulses’ width is about 27-28 ms. Following that are detailed images of my clock rising edge (about 2us) and falling edge (0.4 us).

enter image description here
Clock rising edge
Clock falling edge

counterbinaryparasitic-capacitance

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edited 12 hours ago

asked 2 days ago

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Thomas Wilk

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  • 2Sounds like your clock source might be the problem. – Kartman 2 days ago
  • 2You could have occasional double clocking. Slow or noisy clock edges can cause two clocks on the positive edge or a false clock on the negative edge. What does your clock look like? – Mattman944 2 days ago
  • 1Stick your bypass close to ship. Where is 3Hz coming from? – StainlessSteelRat 2 days ago
  • 1You must generate your clock from a clean source, like an oscillator, or a switch debounce buffer. Using a plain switch will generate many extra pulses, giving you the symptoms you see. – Neil_UK 2 days ago
  • 1Decoupling capacitors are always needed for digital or analog circuits … clk rise time 15us max. – Antonio51 2 days ago 
  • CD4029 is a bit complicated. So I skimmed the datasheet and made a cheatsheet: imgur.com/gallery/unyrXMJ – tlfong01 yesterday  
  • 1@Mattman944 I will post an image of my clock. It is a 0 – 12V signal coming from a 555. The pulse width of the clock is about 27-28 ms, with about 50% duty cycle. I do not see any clock irregularities. Currently I have my pin 3 (555 output) shorted to the clock input of the 4029. – Thomas Wilk yesterday
  • 1@StainlessSteelRat how do you determine what bypass cap to use “close” to the chip? I tend to try values starting small and then going larger until I see something that works. Any recommendations? – Thomas Wilk yesterday
  • 5We need to see this clock with a 500ns/div timescale. Two captures are needed: one of the rising edge, another of the falling edge. Also, decoupling caps for both 555 and 4029 can be just 0.1uF, connected directly across the supply input pins. Nothing bigger is needed, just maybe 10uF-100uF bulk capacitor between the voltage rails on the breadboard. Tweaking the capacitors beyond that won’t improve things. Post a picture of the breadboard so that we can see all the connections. Most likely the breadboard layout is goofy. I’ve put together your circuit and it works fine. So the idea is ok. – Kuba hasn’t forgotten Monica yesterday 
  • 2We also need to see an accurate schematic of your circuit. For example, is there a capacitor between VC and GND on the 555 chip? Are pins 2 and 6 connected together? Etc. The breadboard pictures must be good enough to trace all the connections, otherwise we can’t check your work. – Kuba hasn’t forgotten Monica yesterday
  • Now I have found a more nice looking datasheet and made a wiring cheat sheet: (1) diarioelectronicohoy.com/blog/imagenes/2020/04/cd4029b.pdf, (2) imgur.com/gallery/c3IZmdQ. – tlfong01 yesterday  
  • 1Your oscilloscope has two channels. Please show the clock together with Q1, where the problem is visible. – CL. yesterday
  • Now I am using a 1 MHz crystal clock to input to the CD4029 and use my 4 channel scope to display Clock, Q1, Q2, and Q3 output. (1) imgur.com/gallery/M4zDW92, (2) imgur.com/gallery/vztSRwd – tlfong01 yesterday  
  • And this is my 1MHz crystal clock: imgur.com/gallery/oASrSNh – tlfong01 yesterday   
  • Now that I have verified that CD4029 binary counter can count 1 MHz square wave signal, with stable 50% duty cycle, next step is to use a low frequency signal perhaps 10Hz (The OP uses 3Hz), and see if the O/P duty cycle is stable. I know NE555 timer module’s signal is not easy to set at very low frequencies, so I will be using the XY PWM sign gen to do the testing: How can Rpi4B python UART talk to XY PWM Signal Generators? – Asked 2 years, 10 months ago, Viewed 979 times raspberrypi.stackexchange.com/questions/104779/… – tlfong01 21 hours ago   
  • So I input XY-PWM’s 10 Hz signal to CD4019 and found its binary counter outputs Q1, Q2, Q3 OK: (1) imgur.com/gallery/OhUFf8e (2) imgur.com/gallery/xjkbwxr – tlfong01 8 hours ago   

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