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I wish calculate the maximum number of samples per second that can be obtained by a particular I2C ADC. The ADC is 12-bit, operating at 400 kHz and in continuous mode. Any ideas? Thanks!adci2csamplingformula-derivationShareCiteEditFollowFlagasked 11 hours agoonlooker1766 bronze badges
- 5If this is not homework question, you should give the reference of that particular ADC and look for its datasheet. – user2233709 11 hours ago
- 2400 kHz is one of the standard I2C bus clock speeds and thus probably unrelated to the chip’s actual sampling speed. – Unimportant 11 hours ago
- 1@user2233709, no this is not homework. This question is based solely on curiosity. The ADC I am using is the AD7992, Datasheet can be found in this link; link – onlooker 11 hours ago
- 1First page: “Fast throughput rate: up to 188 kSPS” (thus, your 400 kHz busspeed is the bottleneck). – Unimportant 11 hours ago
- 1@Unimportant, yes, I noticed that, but let’s say I decrease the bus speed to 100 kHz what is the MAX sps I can get? – onlooker 11 hours ago
- 1Approximately sampling clock freq after prescaling / no. of sampling cycles … – Meenie Leis 11 hours ago
- 1@MeenieLeis, Thanks for your answer. How can I obtain these? – onlooker 11 hours ago
- 1@onlooker With a quick glance at the datasheet it looks like it takes writing 1 byte to the device to select the result register and then reading 2 bytes to get the result. How many times per second can you transfer 3 bytes over 100kHz I2C? – Unimportant 11 hours ago
- 1@Unimportant, 12.5k times per second? – onlooker 11 hours ago
- 2Guessing 2 bytes + 2 ack bits, 9 + 9 = 18 cycles of 100 kHz clock, so 5.5 kSps. The same value is there on data sheet as well. – Meenie Leis 11 hours ago
- 2100000 / (9 clocks per byte * 3) = 3.7k. Adding overhead such as start and stop conditions will lower that even further. – Unimportant 10 hours ago
The datasheet indicates two modes at 400kbps Clk:
21ksps and 22ksps.
2 bytes + 2 ack bits, 9 + 9 = 18 clock cycles .
- 1It’s pretty lame when someone votes -1 and is afraid to comment. Those people cannot read either. The datasheet tells you the answer on p3. Reading and writing is just a skill some people lack but courtesy is expected. – Tony Stewart EE75 4 hours ago
- 1I think the OP does not quite understand the operation of the ADC, particularly the meanings of “continuous mode” (vs “single shot” mode), “max sample rate” etc. However, I think his question is concise and clear, and Tony’s answer is good. Many people cannot” read the datasheet, because they don’t have the prerequisite technical knowledge of reading general timing diagrams, particularly I2C timing ones. – tlfong01 4 hours ago
- And even if one knows how to read I2C/SPI timing diagrams, he needs to know much more: the ADC operations involved, such as (1) The algorithm of SAR and (2) How to use the hardware (a) track/sample and hold the analog voltage to convert, (b) How to use a DAC and comparator to do binary search for the SAR. (3) I would recommend the OP to read the Maxim Integrated newbie friendly tutorial: Understanding SAR ADCS: Their Architecture and Comparsion with other ADCS, Tutorial 1080 – Maxim Integrated. maximintegrated.com/en/design/technical-documents/tutorials/1/… – tlfong01 2 hours ago
- 1The datasheet table of specs clearly defines ksps for example clock rates. How hard is that? – Tony Stewart EE75 1 hour ago
- Well, I very much agree with you that the OP’s question is trivial and straightforward, and of course very clear. I also find it very easy to write up a short, generic answer like yours, without any need to know or refer to which ADC the OP is using. I just use the datasheet of any popular I2C/SPI SAR 10/12/16-bitADC and show the OP which section to read for the answer, and the OP should generalize my answer and apply it to any particular ADC. However, the thing is that if the OP does not have the prerequisite/background knowledge, then my short answer won’t help. – tlfong01 1 min ago Edit