mosfet linear mode and linear region

MOSFET terminology seems to vary in every article i read!

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For someone trying to learn about FET’s, it seems there is no consistency in terminology (unless i am reading things wrong?)

Trying to understand a FET as a switch (for power applications). It has become clear that you want to operate a switch in the ohmic region. To get to the ohmic region you would need to go from cut off -> saturation -> ohmic region.

TI refers to it like this in an app note: https://www.ti.com/lit/ml/slua618a/slua618a.pdf?ts=1613979703351&ref_url=https%253A%252F%252Fwww.google.si%252F

Snippet from a TI application note

From this I implied that the ‘linear’ region is in fact rather confusingly the saturation region of the FET as shown all across the web for a FET curve:

enter image description here

However, when i go to wikipedia i came across the following image:

enter image description here

This is saying the exact opposite of what i understood which is saying the ohmic region is the linear region?

Infineon has an app note around FET switching, titled linear mode operation (https://www.infineon.com/dgdl/Infineon-ApplicationNote_Linear_Mode_Operation_Safe_Operation_Diagram_MOSFETs-AN-v01_00-EN.pdf?fileId=db3a30433e30e4bf013e3646e9381200#:~:text=Many%20applications%20exist%20with%20the,to%20source%20(VGS)%20voltage.)

They refer to the linear mode as saturation region as shown from this :

enter image description here

So what is it then?

Also just to be clear is the reason we want to minimise time in the saturation region as a FET because here we have a VDS and an ID current flowing through the FET? Whilst as soon as the fet reaches linear region, it’s VDS would fall close to 0 and hence minimise losses?

When we say the FET is saturated, it means for a given vgs, vds makes no difference to drain current (because channel can’t let more electrons to flow?) Shouldn’t the ohmic region be called saturated? Since increasing VGS makes no difference to drain current as the ID is now limited by the circuit and not the FET?

Edit: Answers in electronic stack exchange say it is the saturation region:


link2mosfetfetsaturationlinear-regionShareCiteEditFollowFlagedited 2 hours agoasked 2 hours agoHasman40414111 silver badge99 bronze badges

  • #Hasman404, When I first read the second paragraph of your question, my impression was that you have mixed up (messed up :)) all the terms/concepts! The root cause of your confusion/inconsistency is that you have not differentiated between linear mode and linear region. So you won’t appreciate that for a MOSFET, you can operate in linear mode in the saturation region. This picture hopefully helps: i.imgur.com/CG5leI1.jpg. Happy thinking! Cheers. – tlfong01 6 mins ago    Edit   

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2 Answers


So what is it then?

This is the correct graph: –

enter image description here

Taken from this wiki page.

Saturation refers to the channel being saturated and, as you said, no matter what VDSVDS you apply, current remains constant. It is sometimes also referred to as the active region (not to be confused with the MOSFET being activated or ON).

The linear (triode) or ohmic region is when the MOSFET is used as a switch (ON). The top graph is basically wrong because it doesn’t correctly show the different slopes in the ohmic region when you apply different gate voltages. This region is called linear because there are different slopes that are governed by the gate voltage and means the MOSFET can act like a variable resistor hence, it gets the name linear but, different texts use this term rather loosely.

Also just to be clear is the reason we want to minimise time in the saturation region as a FET because here we have a VDS and an ID current flowing through the FET? Whilst as soon as the fet reaches linear region, it’s VDS would fall close to 0 and hence minimise losses?

Yes, we want to minimize time in the saturation region because that is when the MOSFET is dissipating the most power and potentially operating below it’s ZTC (zero temperature coefficient) and may suffer rapid thermal runaway.

Shouldn’t the ohmic region be called saturated?

No, because in the ohmic region the channel isn’t saturated. However, for a BJT, that equivalent part of the characteristic is called the saturation region but, for different reasons; for a BJT, it is the base that becomes saturated. Same name, different mechanism, different part of the characteristic.ShareCiteEditFollowFlagedited 2 hours agoanswered 2 hours agoAndy aka330k1818 gold badges266266 silver badges575575 bronze badges

  • The two links i have provided refer to saturation as the linear region. Also is TI in the snippet and link to the app note not referring to the linear region as the saturation region when they say ‘it must go through it’s linear region’. – Hasman404 2 hours ago
  • The so-called “linear” region does tend to be misused in some texts. And, I think that’s because in a BJT, the saturation is sometimes referred to as the linear region. People forget that BJTs and MOSFETs (despite having similar looking characteristics) have a different saturation mechanism. – Andy aka 2 hours ago
  • That is really annoying.. Infineon has a FET application note called linear operating mode (infineon.com/dgdl/…) They also refer to saturation as the linear region! – Hasman404 2 hours ago
  • Many share @Hasman404 ‘s confusion. I think it stems from the simple fact that (on your graph) the linear region is populated with curved lines (non-linear), whilst the saturation region is populated with straight lines (linear). It’s just exacerbating the confusion… – Paul Uszak 1 hour ago
  • @PaulUszak those straight lines you mention are the most non-linear part of the MOSFET characteristic. The curved lines (despite them being curved) are more linear in terms of ohms law. – Andy aka 1 hour ago

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Your answer is approximation.

The following is a graph of output characteristics for an arbitrary 2N7000 MOSFET:-


Assume a fixed gate drive VGSVGS of 5V and ignore all the other curves. So it’s fixed. Consider the MOSFET then as an opaque component with only two legs, Drain and Source.

As VDSVDS (voltage across component) changes, IDID (current through component) changes. And they change almost linearly if you squint sideways at my graph (purple line). Like a resistor. The first part increases linearly, and then goes flat at saturation when it no longer behaves as a resistor. These are approximations, but form the basis of the terminology in your question. The difference is simply real world characteristics being more complex than theoretical approximations. And confusing graphs.

Actually the initial slope is ∝VGS−VT∝VGS−VT where VTVT is the threshold voltage.ShareCiteEditFollowFlaganswered 50 mins agoPaul Uszak6,37633 gold badges2828 silver badges5656 bronze badgesAdd a comment

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