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Re-configure SPI-CS as gpio while using SPI

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I am on a raspberry pi 4. Using both SPI’s with no need for either chip select. I’m running out of I/O and could really use those. Does anyone know if there is a way to repurpose the SPI chip selects as gpio while still using SPI? Thank you for your time!gpiopi-4spidevice-treeShareEditFollowCloseFlagasked 9 hours agochrismec311 bronze badge New contributorAdd a comment

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If you are not using them for SPI you can use them for any of their alternative functions. So yes, just set them to INPUT mode or OUTPUT mode using the GPIO library of your choice.

However the current Linux SPI driver leaves them in OUTPUT mode as it drives the select lines itself. You might have to use a different SPI driver.

If you are using pigpio set the ux bit to 1 for each GPIO you don’t want to be used as a SPI chip select.

u2 is only relevant to the auxilary SPI. u0 and u1 are used by both SPI devices.

If you are using the standard SPI driver perhaps select a GPIO not available on the expansion header.

e.g.

dtoverlay=spi0-2cs,cs0_pin=44,cs1_pin=45ShareEditFollowFlagedited 3 hours agoanswered 8 hours agojoan61.5k55 gold badges5858 silver badges9393 bronze badges

  • Which leads to the next question… 🙂 – Seamus 6 hours ago
  • The stars have aligned as I’m already using PIGPIO! I’m not quite understanding the spi flag setup for ux though. Is each ux bit for the associated CE? Where first cs on main spi would be u0 and 2nd would be u1? Then for aux spi its the same but it has three cs’s so u2 would be in use as well. Am I understanding that correctly? – chrismec 5 hours ago
  • Awesome! Thank you very much : ) – chrismec 2 hours ago
  • I’m guessing pigpio uses the standard spi driver when not bit banging. I was not able to use CE0 as a gpio simply by setting the ux bits to 1. Changing the chip selects to IO not available on the header with dtoverlay cleared that up though. Thanks again to all yall. – chrismec 40 mins ago

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If you’re using RaspiOS 32 with the latest 5.10.11 kernel then you have /boot/overlays/spi0-1cs.dtbo and /boot/overlays/spi1-1cs.dtbo

Those free up the second CS pin. There’s even an option to free up the MISO pin if you’re doing send-only SPI transfers.

From /boot/overlays/README

Name:   spi0-1cs
Info:   Only use one CS pin for SPI0
Load:   dtoverlay=spi0-1cs,<param>=<val>
Params: cs0_pin                 GPIO pin for CS0 (default 8)
        no_miso                 Don't claim and use the MISO pin (9), freeing
                                it for other uses.

Name:   spi1-1cs
Info:   Enables spi1 with a single chip select (CS) line and associated spidev
        dev node. The gpio pin number for the CS line and spidev device node
        creation are configurable.
        N.B.: spi1 is only accessible on devices with a 40pin header, eg:
              A+, B+, Zero and PI2 B; as well as the Compute Module.
Load:   dtoverlay=spi1-1cs,<param>=<val>
Params: cs0_pin                 GPIO pin for CS0 (default 18 - BCM SPI1_CE0).
        cs0_spidev              Set to 'disabled' to stop the creation of a
                                userspace device node /dev/spidev1.0 (default
                                is 'okay' or enabled).




ShareEditFollowFlaganswered 3 hours agoDougie4,41544 gold badges1010 silver badges2222 bronze badges

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