I’m trying to understand this MOSFET circuit which creates negative resistance. Whilst the paper explores how it works, I’m not really understanding it. I’ve tried simulating it in SPICE however I’m not really seeing the negative resistance effect, i.e negative current is proportional to voltage. A general overview of this circuit would be greatly appreciated as well as some indication of how to recreate it in LTSpice would be handy.
Equally any more examples of MOSFET based negative resistance would be helpful to understand it deeper.
- It’s not clear from that circuit where the pickoff point is, and you worry me with your wording “negative current is not proportional to voltage”. If you do a DC sweep and plot the current vs. voltage, you should see that it has a negative slope at some point in that curve. That negative slope — not necessarily a perfect 0-centered straight line with negative slope — is considered “negative resistance”. – TimWescott yesterday
- 2You understand it’s negative differential resistance, right? – Justin yesterday
- @TimWescott Yes, my bad, I meant to say “negative current is proportional to voltage” in relation to that negative slope that you have mentioned. Even so, what I did mean was also a poor choice of words to explain but I hoped people would get the gist. – kepsek yesterday
- Why does Q1 have no body terminal? – Tony Stewart Sunnyskyguy EE75 23 hours ago
- @kepsek, (1) To understand “negative resistance”, you must first define it, (2) To define something, you must first define the “terms” used, (3) For (1) and (2), I would suggest to Wki, Negative resistance – Wikipedia en.wikipedia.org/wiki/Negative_resistance. (4) To test if you do “understand” negative resistance, you should close the “book” and tell me a couple of critical terms/definitions you have just read in the Wiki. For example you might start your list with with the term “differential”, and use you own words to define it (with the book closed, :), / to continue, … – tlfong01 21 mins ago
- (5) Forget the IEEE 1948 paper for now, because you first need to understand the 70 year old terms and conditions used there, which are outdated/obsolete. (6) To understand why the three N-FET circuit is dynamically, dfferentially negatively resistive, you need to understand thoroughly the N-FET characteristic and operation, (7) Again, after studying the circuit, you must list some critical ideas “between the lines”, or more precisely, “among the circuit symbols in the schematic”. Let me ask you an example question: (a) Why Q1′ G and S are shorted? Explain in a couple of sentences pls, … 🙂 – tlfong01 5 mins ago Edit
Say you increase the voltage at VDSVDS. This increases the voltage on Q2’s gate, increasing the conductivity of its channel, lowering the voltage at VGSVGS. This decreases the current through Q3’s channel. So by increasing the voltage VDSVDS you’ve decreased the current that the VDSVDS supply must provide, which is the definition of a negative resistance load.
Of course this all depends on Q1, Q2, and Q3 being in the appropriate operating modes, so there will be a limited range of voltages over which the negative resistance behavior can be observed.
negative current is not proportional to voltage.
If you apply a positive voltage to a circuit branch and it sends current back out towards you (“negative current”) then that branch is delivering power to you, not absorbing power from you.
This circuit doesn’t do that.
But it does have a region where dVDSdIDS<0dVDSdIDS<0, which is what the authors are referring to as negative resistance (and also what we call negative resistance in the case of common negative-resistance elements like glow tubes and Esaki diodes).shareedit follow flagedited 8 hours agoanswered yesterdayThe Photon110k33 gold badges137137 silver badges259259 bronze badges
- Also to clarify: “negative resistance” in this case refers to negative differential resistance i.e. a rise in voltage across the component results in the current through the component dropping to a smaller but still positive value. – vir yesterday
- What conditions create -Vdd/Idd for a small signal? – Tony Stewart Sunnyskyguy EE75 yesterday
- I think you have a typo. dV/dI < 0, not dI/dV < 0. – Mitu Raj 11 hours ago
- 1@MituRaj, thanks. I actually thought about which way it should be when I was writing it and still somehow got it wrong. – The Photon 8 hours ago
(I dedicate my answer to @tlfong01 in gratitude for his responsiveness.)
This is a typical example of how a simple idea can be presented in an insanely complex way to become a scientific article…
This kind of negative resistance is named “negative differential resistance” (NDR). Actually, it is “over dynamic resistance” (I have revealed the truth about it in https://en.wikibooks.org/wiki/Circuit_Idea/Negative_Differential_Resistance).
Devices such a tunnel diode possesses such an N-shaped IV curve. Here it is artificially obtained. The trick to create the negative resistance region is simple – driving a MOSFET (Q3) both from the side of the drain and gate. Thus, when Vd increases, Q3 is forced (from the side of the gate) to increase enough its dynamic “resistance” so that Id decreases despite the fact that Vd increases.
This can be explained by Ohm’s law written in a form of Id = Vd/Rds where Rds is the dynamic “resistance” between the Q3 drain and source. In this expression, when the numerator (Vd) increases, the numerator (Rds) also increases… and to an even greater extent. So, their ratio (Id) decreases.
In other words, the trick is that, in Ohm’s law, the current is a function of two variables – both voltage and resistance… and thus its direction of change is reversed.
It only remains to answer the question, “What is the point of all this?”shareedit follow flagedited 4 hours agoanswered 4 hours agoCircuit fantasist5,02811 gold badge88 silver badges2222 bronze badgesadd a comment