I want to get Analog Audio Input using a PCM1802 ADC Module and MAX4466 microphone module using python. It is actually a project for a very basic and introductory course about Arduino and AVR assembly and as the last part, it wants us to completely figure out how Raspberry Pi works! (I know it may sound very weird that an Arduino course with AVR assembly has a Raspberry Pi Python project!)
We are given a CJMCU PCM1082 ADC Module and a MAX4466 microphone.
CJMCU PCM1082 ADC Module has SCK,PDW,LRCK,FSY,BCK,DOUT,GND,3.3V,5V pins also with LIN and RIN.
Connecting the 3.3,5 and GND are pretty obvious, but for the other ones, I read the PCM1802 IC datasheet that is used in the module, And I found out that:
- SCK is System clock input
- PDW is Power-down control which is active low.
- LRCK is Sampling clock input and output
- FSY is Frame synchronous clock input and output
- BCK is Bit clock input and output
And DOUT is simply serial output.
As I said, the course was about Arduino and I am completely new to Raspberry Pi. I want to know how I should connect these pins to Raspberry Pi pins and what setting (Setups) should I do in Python for them to work properly? I searched the Internet for some tutorials and I just found some about MCP3008. Unfortunately it just has one clock pins but this PCM1802 ADC has three clocks and some other things and I don’t know how should I connect and setup them.
You can see the pictures of ADC module and MAX4466 microphone module below:
I am a PCM1802 24-bit ADC newbie, never used it before. It is a complicated device and its operation needs long explanation. For now, I am only trying to give quick and dirty short answers to the OP’s couple of questions. I hope to give longer answers later.
All newbies wishing to fully understand the answers given here, are expected to spend hours, yes, hours, not minutes, to google, wiki, to read and digest the references and particularly the appendices below:
(1) How come MCP3008 has only one clock, but PCM1802 three?
Well, [In slave mode] BCK, LRCK, and FSYNC are input pins, as summarized below (See Datasheet Section 7.4.4 Slave Mode for more details):
(a) FSYNC enables the BCK signal, and the device can shift out the converted data while FSYNC is HIGH. (b) The delay of FSYNC from the LRCK transition must be within 16 BCKs for the 64-fS BCK format and within 12 BCKs for the 48-fS BCK format.
(2) How can Rpi config and control the PCM1802?
Ah, you can use Rpi GPIO pins to do config and control, as summarized below:
(a) BCK, LRCK, and FSYNC clock signals to control output timing (Section Section 184.108.40.206, Also Appendix E below.) (b) PDWN, controls the entire ADC operation. (c) BYPAS, to bypass DC component rejection (d) OSR, to set over sampling rate ratio of the delta-sigma modulator, ×64 or ×128 (e) FMT1 and FMT0, to four audio data formats in both master and slave modes.
PS – I forgot to point out two things:
(1) MCP3008 uses SPI interface, and the clock you see is the SPI Clock. PCM1802, on the other hand, does NOT use any serial interface, therefore no SPI clock, and three control clocks as summarized below.
(2) Rpi working as a DSP (Digital Signal Processor) uses GPIO signals as clocks to control the output timing (time multiplexing the left and right audio output as a serial signal) of PCM1802 which works as a slave. Rpi GPIO signals are also used to config the PCM1802 operation mode and data formats. But you can also by hand, short the little soldering pads to do permanent configuration.
Appendix A – PCM1802 Block Diagram
Appendix B – PCM1802 Pinout
Appendix C – PCM1802 Module Features
Appendix D – PCM1802 Application Example
Appendix E – PCM1802 Datasheet Reading Summary
7.3.1 Hardware Control The FMT0, FMT1, OSR, BYPASS, MD0, and MD1 pins allow the device to be controlled by tying these pins to GPIO and GND or VDD from a host IC. These controls allow full configuration of the PCM1802.
7.3.3 System Clock The PCM1802 supports 256 fS, 384 fS, 512 fS, and 768 fS as the system clock, where fS is the audio sampling frequency. The system clock must be supplied on SCKI.
7.4.1 Power Down, HPF Bypass, Oversampling Control
PDWN controls the entire ADC operation. During power-down mode, both the supply current for the analog portion and the clock signal for the digital portion are shut down, and power dissipation is minimized. DOUT is also disabled and no system clock is accepted during power-down mode.
BYPAS – the built-in function for DC component rejection can be bypassed using the BYPAS control. In bypass mode, the DC components of the analog input signal, such as the internal DC offset, are converted and included in the digital output data.
OSR controls the oversampling ratio of the delta-sigma modulator, ×64 or ×128.
7.4.2 Serial Audio Data Interface The PCM1802 interfaces with the audio system through BCK, LRCK, FSYNC, and DOUT.
220.127.116.11 Data Format The PCM1802 supports four audio data formats in both master and slave modes, and they are selected by FMT1 and FMT0.
18.104.22.168 Synchronization With Digital Audio System In slave mode, the PCM1802 operates under LRCK, synchronized with system clock SCKI. The PCM1802 does not require a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI.
7.4.3 Master Mode
In master mode, BCK, LRCK, and FSYNC work as output pins, and these pins are controlled by timing which is generated in the clock circuit of the PCM1802. FSYNC is used to designate the valid data from the PCM1802.
The rising edge of FSYNC indicates the starting point of the converted audio data and the falling edge of this signal indicates the ending point of the data. The frequency of this signal is fixed at 2 × LRCK. The duty cycle ratio depends on data bit length. The frequency of BCK is fixed at 64 × LRCK.
7.4.4 Slave Mode
In slave mode, BCK, LRCK, and FSYNC work as input pins. FSYNC enables the BCK signal, and the device can shift out the converted data while FSYNC is HIGH. The PCM1802 accepts the 64-fS BCK or the 48-fS BCK format. The delay of FSYNC from the LRCK transition must be within 16 BCKs for the 64-fS BCK format and within 12 BCKs for the 48-fS BCK format.
7.4.5 Interface Mode The PCM1802 supports master mode and slave mode as interface modes, and they are selected by MODE1 and MODE0 as shown in Table 9.
22.214.171.124 Control Pins
The FMT, MODE, OSR, and BYPASS control pins are controlled by tying up to VDD, down to GND, or driven with GPIO from the DSP or audio processor.
126.96.36.199 DSP or Audio Processor
In this application (Appendix D above) a DSP or audio processor acts as the audio master, and the PCM1802 acts as the audio slave. This means the DSP or audio processor must be able to output audio clocks that the PCM1802 can use to process audio signals.
Appendix F – Interface Timing
End of Answer