Update 2019feb03hkt2157 – Latch Up References

Latch-up – Wikipedia

A latch-up is a type of short circuit which can occur in an integrated circuit . More specifically it is the inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit, triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its destruction due to overcurrent.

The parasitic structure is usually a PNPN structure which acts as a PNP and an NPN transistor stacked next to each other. During a latch-up when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it.

The latch-up does not have to happen between the power rails – it can happen at any place where the required parasitic structure exists. 

A common cause of latch-up is a positive or negative voltage spike on an input

or output pin of a digital chip that exceeds the rail voltage by more than a diode drop.

Another cause is the supply voltage exceeding the absolute maximum rating, often from a transient spike in the power supply. 

It leads to a breakdown of an internal junction.

Parasitic structure – Wikipedia

In a semiconductor device, a parasitic structure is a portion of the device that resembles in structure some other, simpler semiconductor device, and causes the device to enter an unintended mode of operation when subjected to conditions outside of its normal range.

For example, the internal structure of an NPN bipolar transistor resembles two PN junction diodes connected together by a common anode. If a sufficient forward bias is placed on this junction it will form a parasitic diode structure, and current will flow from base to collector.

A common parasitic structure is that of an SCR. Once triggered, an SCR conducts for as long as there is a current, necessitating a complete power-down to reset the behavior of the device. This condition is known as latchup.

Connecting GPIO pin through 10k to 5V
Rpi’s GPIO pins are not 5V tolerant, which means 5V is fatal…

Rpi GPIO Latch Up Discussion

The article in the appendix below has an explanation on why you should not connect a GPIO pin to 5V through a resistor.

I think either of the two situations below has the risk of latching up the GPIO pin and may cause severe damage to Rpi.

(1) Setting input mode to a GPIO pin which is connected to the input pin of a low trigger relay, because essentially you are connecting the GPIO pin to the 5V through the relay coil (X), and the transistor Collector Base junction (Y), and resistor + LED (Z) (see schematic below).

(2) Connecting GPIO pin to 5V through a resistor.

Appendix – Warning on dangerous pulling up GPIO pin to 5V

GPIO Electrical Specifications Raspberry Pi input and output pin voltage and current capability – Mosiac Documentation Web

GPIO pin circuitry

The internal diodes shown in the figure are not really substrate diodes, but they are actually parasitic FETs.

Electrically, their I-V characteristic looks like a diode’s, but with a greater forward drop and a more gradual knee.

They may protect against low current transient events caused by transient out-of-range voltages applied to the pins, but they are not intended to protect against the application of voltages greater than the supply voltage or less than ground, even with an external series resistor.

In brief, you should never deliberately forward bias those “diodes”. Consequently, you can not safely place an external pull-up resistor to 5V on the I/O pin. That would forward bias a parasitic FET and owing to its poor internal impedance to the chip’s internal power rail it may overheat, or worse, it may bias up parts of the chip to voltages greater than they can handle.

So, don’t do it!


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