RE: RASPBERRY PI + RELAY GPIO DONT WORK
Postby tlfong01 » 2019-Feb-07 Thu 10:38 pm
tlfong01 wrote: ↑
2019-Jan-29 Tue 9:32 pm
Dam_Fr wrote: ↑
2019-Jan-29 Tue 4:24 pm
I have some 3.3K and 10K resistances, I must connect a 10k resistance between GPIO PIN 40 and 5V ?
Connecting GPIO pin through 10k to 5V
Rpi’s GPIO pins are not 5V tolerant, which means 5V is fatal…
Rpi GPIO Latch Up Discussion
The article in the appendix below has an explanation on why you should not connect a GPIO pin to 5V through a resistor.
I think either of the two situations below has the risk of latching up the GPIO pin and may cause severe damage to Rpi.
(1) Setting input mode to a GPIO pin which is connected to the input pin of a low trigger relay, because essentially you are connecting the GPIO pin to the 5V through the relay coil (X), and the transistor Collector Base junction (Y), and resistor + LED (Z) (see schematic below).
(2) Connecting GPIO pin to 5V through a resistor.
Appendix – Warning on dangerous pulling up GPIO pin to 5V
GPIO Electrical Specifications Raspberry Pi input and output pin voltage and current capability – Mosiac Documentation Web
http://www.mosaic-industries.com/embedd … ifications
GPIO pin circuitry
The internal diodes shown in the figure are not really substrate diodes, but they are actually parasitic FETs.
Electrically, their I-V characteristic looks like a diode’s, but with a greater forward drop and a more gradual knee.
They may protect against low current transient events caused by transient out-of-range voltages applied to the pins, but they are not intended to protect against the application of voltages greater than the supply voltage or less than ground, even with an external series resistor.
In brief, you should never deliberately forward bias those “diodes”. Consequently, you can not safely place an external pull-up resistor to 5V on the I/O pin. That would forward bias a parasitic FET and owing to its poor internal impedance to the chip’s internal power rail it may overheat, or worse, it may bias up parts of the chip to voltages greater than they can handle.
So, don’t do it!
latching_up_risk_2019feb0701.jpg (172.2 KiB) Viewed 463 times